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Espressif Systems /ESP32 /TIMG0 /INT_ST_TIMERS

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Interpret as INT_ST_TIMERS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (T0_INT_ST)T0_INT_ST 0 (T1_INT_ST)T1_INT_ST 0 (WDT_INT_ST)WDT_INT_ST 0 (LACT_INT_ST)LACT_INT_ST

Fields

T0_INT_ST

interrupt when timer0 alarm
T1_INT_ST

interrupt when timer1 alarm
WDT_INT_ST

Interrupt when an interrupt stage timeout
LACT_INT_ST

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Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data